The invention relates to a circuit arrangement for a video recorder, with a separation circuit which, after reception of a release signal, separates the video program system data (VPS data) contained in a television signal and synchronized with a first clock signal and which, after checking the VPS data for freedom from errors, generates a control signal; with a switch which, in its first position that is present at least at the beginning of the data line, feeds a second clock signal, synchronized with the first clock signal, to a counter for measuring the intervals of the television sync pulses and in a second position feeds the sync pulses to the counter for counting the sync pulses; with a field (half-frame) identification circuit that evaluates the counter position and at the beginning of the first half-frame generates an identification signal which sets the switch from the first to the second position and which, after detection of the data line, releases the data line decoder that evaluates the counter position and generates the release signal; and with a gating circuit which generates a test signal and which, upon the appearance of the identification signal, sets the test signal to a first state and, upon the appearance of the control signal, sets it into a second state.
The Video Program System (VPS) serves for controlling the recording operation of video recorders. In line 16 of a television frame, the transmitter sends out data (VPS data) that identify a transmission. These VPS data are decoded in the video recorder and compared with the data entered and stored by the user. If the data agree, the video recorder starts recording. This form of input-controlled recording prevents misrecordings which, upon a change in program transmission, occur with respect to the announced end of transmission (over-running, contribution exchange).
In line 16, the data information consists of fifteen words, each containing 8 bits. The binary information is transmitted in biphase code at a data rate of 2.5 Mbit/s. The words eleven to fourteen are provided for the VPS data. Further information will be found in "Rundfunktechnischen Mitteilungen", Vol. 0.29, 1985, No. 4, pages 161 to 169.
The aforementioned circuit arrangement is used in the SAF 1134 P integrated circuit. This circuit decodes the VPS data, and in addition, delivers a test signal that indicates whether a television transmitter is transmitting VPS data and whether the data are being received free from errors. After the switch-over has taken place from the second to the first half-frame, the half-frame identification circuit generates an identification signal by means of which the test signal is set by the gating circuit into the first state and indicates that no VPS data are available. If error-free VPS data are present, the separation circuit generates a control signal which, at the end of line 16, sets the test signal into the second state. When the data are error-free or VPS data are not available, the test signal remains in the first state. These operating conditions can be displayed optically by means of a light-emitting diode to which the test signal is applied.
If the television signal is interrupted, the test signal remains in the state in which it happens to be at the time. Nor does the state of the test signal change when interference pulses appear. If, for example, interference pulses appear during the second state of the test signal, the test signal remains in this state and thereby indicates that processing of the VPS data is possible although no VPS data are being processed.